Abstract
The Generalized Integrated Interleaved (GII) codes nest short Reed-Solomon (RS)/ BCH sub-codewords to generate codewords of stronger RS/BCH codes. They can achieve hyper-speed decoding and good error-correcting performance with low complexity, and hence are one of the best candidates for next-generation terabit/s communications and storage. The key-equation solver (KES) of the nested decoding for correcting extra errors limits the achievable clock frequency and contributes to a significant portion of the decoder area. This paper summarizes our recent work on hardware architecture design for the nested KES. The clock frequency bottleneck is first eliminated by reformulating the nested KES and exploiting architectural transformations. Then the complexity of each processing element (PE) in the nested KES architecture is reduced by a scaled nested KES algorithm. Furthermore, the number of PEs is reduced by exploiting the data dependency and analyzing the minimum number of coefficients to keep for the involved polynomials.
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