Efficient multiplier structure for realization of the discrete cosine transform

Abstract

This paper presents an efficient serial–parallel multiplier algorithm that realizes the input data bit-serially, for implementation of the discrete cosine transform (DCT), which realizes the input data bit-serially. First, the DCT equation is split into a few groups of equations by using some mathematical techniques, and index tables are constructed to facilitate efficient data permutations. A new formulation of the DCT is then derived. Second, we represent the cosine coefficient in binary form and realize multiplications using a new serial–parallel multiplier architecture that results in a simple structure for VLSI realization.