Efficient multiplication architecture over truncated polynomial ring for NTRUEncrypt system

Abstract

Truncated polynomial ring has important applications in cryptography. It was probably first used in NTRU public key cryptosystem which is one of the most well-known post-quantum cryptosystems. Recently it is found that a modification to NTRU supports somewhat fully homomorphic encryption where a slightly different truncated polynomial ring is adopted. In this paper an efficient architecture is proposed for multiplication over truncated polynomial ring with application for NTRUEncrypt system. The proposed multiplier is based on the compact structure of a modified linear feedback shift register (LFSR) which can reduce the latency for small input polynomial. The compact-designed arithmetic unit capable of performing both modular addition and subtraction takes input from either of two registers on the left hand side. FPGA simulation results show that the product of area and latency for the proposed multiplier is at most 84% compared to any existing work in comparison.