Efficient MODEM Design For SDR Application

Abstract

Efficient modulation and demodulation(MODEM) design is required and essential for Software defined radio (SDR) application. In the proposed design not only reducing the hardware complexity but it will reduce the power consumption also. Optimization of the MODEM hardware is done through three important design metrics through time (speed / frequency), power consumption and area(size). To develop a product that can transmit the signal to a longer distance without loss of original information with high bandwidth. Also to develop a smart MODEM system that can consume very less area and power. The project aims at presenting a method to design an efficient QPSK modulator and demodulator system with and without AWGN(Additive white Gaussian Noise) and RRC filter (Root Raised cosine filter) for SDR application. The entire QPSK system has been simulated in Xilinx 14.7 version software and Vivado software. Finally implemented on to the Spartan 6 FPGA Board and Zynq 7000 based ZED board. the results depicts that the proposed design can greatly improve the speed and reduce the latency and improve the frequency of operation about 20% when compared with the existing method.