Abstract
In this paper, we present an analytical model for fully integrated CMOS narrow-band low noise amplifiers (LNA) that enables rapid design space exploration during the synthesis process. The analytical model captures the impact of parasitics on passive components and devices to accurately predict both impedance matching and noise figure. Our results indicate that the model provides on average 39.8% better accuracy in noise figure than several current analytical modeling techniques with five orders of magnitude improvement in simulation time when compared with a circuit-level simulator. Given its speed and accuracy, our LNA model is well-suited for design space exploration.
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