Abstract

Frequency multipliers are an attractive solution for signal generation in CMOS near and above cutoff frequencies $(f_{\max})$ of active devices. This work focuses on nonlinear transmission line (NLTL) based frequency multipliers, which can be employed for high output power and broadband operation. The performance of an NLTL-based multiplier is limited by the phase mismatch at frequencies of interest caused by dispersion. We propose an alternate NLTL and engineer dispersion to eliminate phase mismatch between desired harmonics. We build two prototypes. First, a 20-GHz frequency doubler is implemented in a 65-nm CMOS process. Second, to show the feasibility of our approach near $f_{\max}$ , a 100-GHz frequency tripler is demonstrated in a 130-nm CMOS process ( $f_{\max} GHz). The achieved conversion loss is 3.5 and 12.2 dB for the doubler and tripler, respectively. The frequency tripler generates maximum power of ${-}{\hbox{1.5}}$ dBm. The relative bandwidth of the doubler and tripler is about 23% and 12.3%, respectively. To the best of our knowledge, the frequency tripler outperforms any previously reported work implemented in a 130-nm CMOS at or above 100 GHz in terms of output power and bandwidth.

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