Efficient methodology for hand-coding video algorithms for VLIW-type processors

Abstract

Digital signal processors (DSP) based on very large instruction word (VLIW) architectures are potentially well suited for software-based implementation of video codecs. In order to achieve real-time performance, the implementation has to be efficiently mapped to the target architecture. Although sophisticated compilers are available for VLIW-type processors, time-critical video coding algorithms can often be more efficiently coded by hand. This is because compilers are still not intelligent enough to fine-tune the organization of data structures or make trade-offs on an abstract algorithmic level. However, hand-coding typically is a very demanding, error-prone and time-consuming task. Exploring as many scheduling opportunities as possible and making the right scheduling decisions is a complex task but is essential for achieving an efficient implementation. In order to address these problems, we have developed a systematic hand-coding methodology which is based on a framework of scheduling heuristics and a directed acyclic graph (DAG) representation with incorporated processor resources. The methodology helps to produce more efficient code in a shorter time compared to ad-hoc hand-coding approaches. Another benefit is that the implementation is well documented through the DAG representation which allows possible modifications to be easily accommodated. The methodology is explained on the examples of two video algorithms, the discrete cosine transform (DCT) and sum of absolute differences (SAD) which have been implemented on the Texas Instruments TMS320C6201 DSP. The performance results confirm the effectiveness of our methodology. The presented methodology may also provide a basis for a visual, semi-automated, interactive developing tool which gives the programmer more control over the implementation of critical algorithms or procedures.