Abstract
In order to improve MQ cryptographic systems on Internet of Things (IoTs) devices, we propose an efficient hardware architecture of Gaussian Elimination in finite fields where area usage is more of a priority. In order to validate our design and verify its effectiveness, an experiment is carried out by using TSMC-0.18 µ m standard cell CMOS Application Specific Integrated Circuit (ASIC), which shows that our design is well suit for MQ cryptographic systems.
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