Efficient Implementation of Sample Rate Converter

Abstract

Within wireless base station system design, manufacturers continue to seek ways to add value and performance while increasing differentiation. Transmit/receive functionality has become an area of focus as designers attempt to address the need to move data from very high frequency sample rates to chip processing rates. Digital Up Converter (DUC) and Digital Down Converter (DDC) are used as sample rate converters. These are the important block in every digital communication system; hence there is a need for effective implementation of sample rate converter so that cost can be reduced. With the recent advances in FPGA technology, the more complex devices providing high-speed as required in DSP applications are available. The filter implementation in FPGA, utilizing the dedicated hardware resources can effectively achieve application-specific integrated circuit (ASIC)-like performance while reducing development time cost and risks. So in this paper the technique for an efficient design of DDC for reducing sample rate is being suggested which meets the specifications of WiMAX system. Its effective implementation also ensures the pathway for the efficient applications in VLSI designs. Different design configurations for the sample rate converter are explored. The sample rate converter can be designed using half band filters, fixed FIR filters, poly-phase filters, CIC filters or even farrow filters.