Efficient HLS Implementation for Convolutional Neural Networks Accelerator on an SoC

Abstract

Convolutional Neural Networks (CNNs) have achieved high accuracy in many applications such as image recognition and classification. However, due to their large amount of parameters and intensive required operations, general purpose processors cannot achieve the desired inference performance levels. Recently, various hardware accelerators for deep CNNs have been carried out to enhance the throughput of CNNs. Among these accelerators, field programmable gate array (FPGA)-based ones have gained a lot of interest due to their high performance, low power consumption, high reconfigurability, and fast development cycle. Furthermore, the availability of high-level synthesis (HLS) tools lowers the programming burden and increases the productivity of the FPGA-based accelerator designers. In this paper, a C++ HLS implementation for FPGA-based accelerator for the convolutional layers of CNNs is proposed. As a case study, we evaluate the proposed accelerator using Resnet50 CNN on Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation board using SDSoC development environment, achieving up to 339x inference speedup.