Efficient High Hamming Distance CRCs for Embedded Networks

J Ray,P Koopman

doi:10.1109/dsn.2006.30

Abstract

Cyclic redundancy codes (CRCs) are widely used in network transmission and data storage applications because they provide better error detection than lighter weight checksum techniques. 24- and 32-bit CRC computations are becoming necessary to provide sufficient error detection capability (Hamming distance) for critical embedded network applications. However, the computational cost of such CRCs can be too high for resource-constrained embedded systems, which are predominantly equipped with 8- bit microcontrollers that have limited computing power and small memory size. We evaluate the options for speeding up CRC computations on 8-bit processors, including comparing variants of table lookup approaches for memory cost and speed. We also evaluate classes of CRC generator polynomials which have the same computational cost as 24- or 16-bit CRCs, but provide 32-bit CRC levels of error detection, and recommend good polynomials within those classes for data word lengths typical of embedded networking applications.

Highlights

Using cyclic redundancy codes (CRCs) for error detection in embedded systems involves a tradeoff among speed, memory consumption, and error detection effectiveness
In addition to studying existing algorithms, we have developed and evaluated techniques which are optimized for a special class of 32-bit CRC checksums that speed up calculations and reduce memory requirements while achieving good error detection performance
We demonstrate the cost of the CRC algorithms in terms of execution time and memory requirements

Summary

Introduction

Using cyclic redundancy codes (CRCs) for error detection in embedded systems involves a tradeoff among speed, memory consumption, and error detection effectiveness. Because many embedded systems have significant resource constraints, it is important to understand the available tradeoff options and, if possible, find ways to attain better error detection at lower computational cost. We identify two new classes of 32-bit CRCs that can be calculated with the same computational cost as existing 16- and 24-bit CRCs while providing improved error detection effectiveness. Computational cost can be a major design factor because of the severe cost constraints on many systems For those applications that must attain high levels of error detection, CRCs are the only practical alternative proven in field use. Frame check sequence (FCS) — the value produced by the CRC computation This digest or checksum provides the redundant information necessary for error detection. The polynomial x8 + x5 + x2 + x1 + x0, which has HD=4 for data words of 18 to 55 bits, will detect all 1-, 2-, and 3-bit errors for those lengths

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Conclusion