Efficient Hardware Architectures for 2-D BCH Codes in the Frequency Domain for Two-Dimensional Data Storage Applications

Abstract

We propose fast and efficient hardware architectures for a 2-D Bose-Chaudhuri-Hocquenghem (BCH) code of size n×n, with a quasi-cyclic burst error correction capability of t×t, in the frequency domain for data storage applications. A fully parallel encoder with the ability to produce an output every clock cycle was designed. Using conjugate class properties of finite fields, the algorithmic complexity of the encoder was significantly reduced, leading to a reduction in the number of gates by about 94% of the brute-force implementation per 2-D inverse discrete finite field Fourier transform (IDFFFT) point for a 15×15, t=2 2-D BCH code. We also designed a pipelined, low-latency decoder for the above encoder. The algorithmic complexity of various pipeline stages of the decoder was reduced significantly using finite field properties, reducing the space complexity of the entire decoder. For a particular case of n=15 and t=2, the architectures were implemented on a Kintex 7 KC-705 field-programmable gate array (FPGA) kit, giving high throughputs of 22.5 and 5.6 Gb/s at 100 MHz for the encoder and decoder, respectively.