Abstract

Several computationally intensive applications in machine learning, signal processing, and computer vision call for convolution between a fixed vector and each of the incoming vectors. Often, the convolution need not be exact because a subsequent processing unit, such as an activation function in a neuron network or a visual unit in image processing, can tolerate a computational error, hence allowing the optimization of the convolution algorithm. This paper develops a method of approximate convolution and quantifies its performance in software and hardware. The key idea is to take advantage of the known fixed vector, view a convolution as a dot product, and approximate the angles between the fixed vector and an incoming vector geometrically. We evaluate the proposed method in terms of the accuracy, running time complexity, and hardware power consumption on the field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) hardware platforms. In a benchmark test, the accuracy of the approximate convolution is 3.7% lower than that of the exact convolution, a tolerable loss for machine learning and signal processing. The proposed method reduces the number of operations in the hardware, and reduces the power consumption of conventional convolution by approximately 20% and the existing approximate convolution by approximately 10%, while maintaining the same throughput and latency. We also test the proposed method on 2D convolution and convolutional neural network (CNN). The proposed method reduces complexity, power consumption for 2D convolution, and power consumption for CNN of the conventional method by approximately 22%, 25%, and 13%, respectively. The proposed method of approximate convolution trades off accuracy with running time complexity and hardware power consumption, and it has practical utility in computationally intensive tasks that tolerate a margin of convolutional error.

Highlights

  • Discrete-time convolution is an important operation in machine learning, signal processing, and computer vision [1]

  • Trading off the computation accuracy, we propose an approximate convolution procedure based on the geometric interpretation of the dot product by approximation of cos θ

  • All state-of-the-art convolution methods, approximate convolution methods, and the proposed method are implemented on field programmable gate array (FPGA) and the 45 nm FreePDK CMOS process with Vivado 2021.2 and Synopsys DC compiler to investigate the area and power utilization

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Summary

Introduction

Discrete-time convolution is an important operation in machine learning, signal processing, and computer vision [1]. The neural network architecture [2] AlexNet [1] uses five embedded convolution layers for image recognition to achieve a recognition rate of 84.7%. ResNet-152 [3] uses 152 convolution layers to improve classification accuracy and achieve a recognition rate of 96.5%. The more convolution layers there are, the better the performance is, leading to a massive use of convolution operations. Extensive convolution improves performance in one area, it undesirably leads to high computational complexity [4] and power consumption. AlexNet takes 1.4 giga operations per second (GOPS) to process a single 224×224-pixel

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