Efficient genetic based topological mapping using analytical models for on-chip networks

Abstract

Network-on-Chips are now the popular communication medium to support inter-IP communications in complex on-chip systems with tens to hundreds IP cores. Higher scalability (compared to the traditional shared bus and point-to-point interconnects), throughput, and reliability are among the most important advantages of NoCs. Moreover, NoCs can well match current CAD methodologies mainly relying on modular and reusable structures with regularity of structural pattern. However, since NoCs are resource-limited, determining how to distribute application load over limited on-chip resources (e.g. switches, buffers, virtual channels, and wires) in order to improve the metrics of interest and satisfy the application requirements becomes a challenging research issue known as topological mapping problem. This paper introduces a topological mapping strategy for direct networks. The Multi-Objective Genetic Algorithm (MOGA) is used to obtain optimal Pareto-front of topological mapping solutions for an arbitrary network topology using a deadlock-free routing algorithm. Considered cost functions are the network latency and power consumption which are accurately estimated through two accurate analytical models. Before using the proposed analytical models in our MOGA method, we validate them through extensive simulation experiments, and compare their accuracy to some known models already proposed in the literature. We then quantitatively and qualitatively compare our analytical model based mapping method to two other methods: a genetic-based and a heuristic. Experimental evaluations using real workloads confirm that the proposed method is cost-efficient and can be used as a powerful tool for NoC design space exploration. Compared to the traditional mapping strategies, our mapping mechanism has the following advantages: (1) it greatly shortens the design period by using analytical models for fast and accurate predictions; (2) it can give a set of solutions, using MOGA, in terms of Pareto-front including, at least one performance-optimal and one power-optimal, and some intermediate solutions; and (3) its runtime is reduced by determining the best generation size based on the used benchmark.