Efficient full data-path width and serialized hardware structures of SPONGENT lightweight hash function

Abstract

In this paper, two efficient low-cost and high-throughput structures of the SPONGENT lightweight hash function are presented. Two structures are called full data-path width (parallel) and 4-bit serialized. The serialized architecture is designed by using one multi-task shift register in the round computations with minimum hardware resources. The area consumed in this structure is lower than that of the full data-path structure but the number of clock cycles is increased. The speed computation of the full data-path is higher compared to the 4-bit serialized structure of the SPONGENT hash function because the data are computed in a parallel form. To improving the timing characteristics, we implement the S-box block as the complex block in the SPONGENT hash function based on an Area×Delay optimized circuit. A large number of gates, in the structure, have been implemented by 2-input NAND and 2-input NOR gates in order to reduce delay and area. The performance measurement of the proposed structures is performed by evaluating the parameters such as area consumption, computation time, critical path delay (CPD), throughput, and throughput/area. The implementation results are achieved for all variants of the SPONGENT hash function in 180 nm CMOS technology. The results of area consumption (for 4-bit serialized structure) and throughput (for full data-path structure) show improvements compared to previous works. For area-constrained applications, the proposed structure with a lower data-path width is an appropriate choice. The full data-path width structure can be used for the high-speed and high-throughout cryptographic applications.