Abstract
Abstract This paper describes a hardware structure for fast Fourier transform (FFT) computation thai is particularly suited to input data presented sequentially. The algorithm allows different representations of complex numbers to be used in the same processing system so that the FFT can be computed by using multiplication-free butterfly elements based on the radix numbers of 2, 3, 4 and 6. In comparison with previous designs in the literature, the new algorithm provides significant hardware savings on the requirements of data memory and multipliers. Furthermore, the FFT size N, which is usually a composite number of 2 or 4, can be more flexible. Efficient data format conversions between different number systems are also provided.
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