Efficient digit‐serial modular multiplication algorithm on FPGA

Abstract

For cryptographic applications, such as DSA, RSA and ECC systems, the crypto-processors are required to perform modular multiplication (MM) on large integers over Galois field. A new digit-serial MM method is presented by using a variable size lookup table. The proposed modular multiplier can be designed for any digit-size d and modulus M which only requires simple operations such as addition and shifting. Based on theoretical analysis, the efficient digit-serial MM architecture requires the latency of $O\lpar \lceil n/d\rceil + d + 2\rpar $ O ( ⌈ n / d ⌉ + d + 2 ) clock cycles. As a result, the developed architecture can achieve less area–delay product on hardware when compared with previous designs.