EFFICIENT DECIMATOR AND INTERPOLATOR ARRAY STRUCTURES

Abstract

New and efficient array processor implementations of polyphase FIR and IIR decimators and interpolators, with integer compression and expansion factors, are derived using an algebraic mapping technique. The technique is based on the time-domain representation of the algorithms. It has the merit of being suitable for describing multirate algorithms. The control signals necessary to implement the polyphase structures are explicitly identified. Different array structures are derived in which the inputs are broadcast or pipelined and outputs are pipelined or added simultaneously. Upper bounds on the input/output processing rates are provided in terms of system parameters and hardware delays. The work is extended to map decimators/interpolators with fractional compression/expansion factors onto systolic hardware structures. The new structures have the advantages of being modular, regular, hierarchical, and pipelined.