Efficient data output from the inner of large size cellular array

Abstract

Efficient data output from large size array structures (such as large size array processor, as may be encountered in single chip large size Artificial Retinas (AR)) is problematic. Wiring cost to connect separately any element of the array is unacceptable. I/O performance are low to access the inner part of the array as I/O are usually done from the border, then moved onto or from the whole structure. This paper describes a structure that implements efficient output of position information at minimal hardware cost. It gives the coordinates of an element of the array that is either in an active state or needs to signal itself. Some solutions have already been proposed, mainly to be able to monitor the activity of array of neurons in a VLSI circuit for perceptive systems. To our knowledge, the structure proposed improves both on compactness and speed over other known methods. Operating principle, structure schematics, simulation and performance issues are presented in this paper. It was first developed to provide high performance output of pixel coordinates, results from images processed in large size digital PARs (Programmable Artificial Retinas). These PARs are single chip optical sensors composed of an SIMD array processor with optical input: a tiny processor is embedded in each pixel of a CMOS image sensor.