Abstract
An integerization technique for creating fixed integer transforms with computationally optimal representations is presented, and the improved performance in embedded systems by employing these integerized implementations is explored. This technique uses an optimal approximation algorithm that finds the lowest-length fractional representation of the rational numbers. The integer transform approximation allows multiplication to be replaced by shift-and-add operations in hardware systems; where multiplication can take several cycles, shifts and adds take one or fewer cycles each. The multiplierless implementation furthermore benefits from employing the proposed method to represent the floating-point coefficients in very high precision requirement areas, like decimation filter design. This paper is strongly oriented around the design of coefficients with hardware constraints in mind, such as minimizing the number of required adds/subtracts and shifts required for some engineering algorithms.
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