Efficient check-node-stopped LDPC decoder design

Abstract

In this paper, we propose a reduced check node operation design for the LDPC decoder. The proposed Check Node Stopping criterion (CNS) reduces the operations of convergent check nodes when the reliability of check node messages that depends on the magnitude of check node messages is larger than a threshold. Thus, the proposed LDPC decoder can can efficiently terminate the redundant check node calculations in the following iterations. From the simulations under the rate-1/2 WiMAX LDPC decoding, the operation of check nodes can be reduced by about 12% at Eb/N0 of 3.6 dB with a small coding coding gain degradation. A 2.85mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> LDPC decoder with CNS is implemented in a 90nm CMOS process. The area overhead of the the CNS is about 0.7% of the total area. The proposed LDPC decoder can decrease 4% power consumption for the stopped check node.