Efficient butterfly inspired optimization algorithm for analog circuits design

Abstract

In this paper for the first time a butterfly inspired optimization algorithm, both in single- and multi-objective version is adapted for analog circuit design. As design examples a two-stage amplifier and a current conveyor are respectively used as a voltage and current mode circuits. For the amplifier, the effects of pole-zero compensation on the stabilization performance is first investigated and then, the proposed approach is used for its optimal sizing. Higher dc gain, larger bandwidth and phase margin are then ensured by this way. For the current conveyor, the effect of channel length and bias current on its main performances is considered. The proposed optimization algorithm allows for a high cut-off frequency and small occupation area. Compared to what previously published, the proposed approach provides better figures of merit for both circuits and can be helpful for the optimal sizing of integrated analog circuits, to meet the challenge of automated design in Very-Large-Scale Integration microelectronic domain.