Efficient backup schemes for processors in embedded systems

Abstract

Embedded processors are often used in safety-critical applications such as automotive engineering. Then a high level of reliability over a long lifetime is a critical demand. Higher levels of integration associated with decreasing feature size and lower signal-to-noise ratios in state-of-the-art digital circuits make vulnerability to dynamic as well as static fault effects more likely than in more robust technologies. Traditional fault-tolerant design technology suffers from several drawbacks. One such example is that the triple redundancy schemes used in avionics are costly, while another is that because only one permanent fault can be recognized and compensated on-line, the second fault may just be noticed. In this paper we present schemes for embedded processors which target a long-term dependability by handling even a series of transient faults in an efficient way. It is based on on-line recognition and repair of non-permanent faults using a roll-back strategy (in short time). For faults that are recognized as permanent, we will discuss possibilities and limitations of reconfiguration or self-repair by using (in-field-)programmable logic devices. This requires the on-line availability of backup devices of reasonable performance and complexity. Methods of how to find functional units suitable for backup strategies will be discussed. To increase the efficiency of a reliable embedded processor structure, we use an application driven reduction strategy for additional test and backup components.