Efficient and robust sharing of memory in message-passing systems

Abstract

An emulation of a wait-free, atomic, single-writer multi-reader register in an asynchronous message passing system is presented. The emulation can withstand the failure of up to half of the processors, and requires O(n) messages (for each read or write operation), assuming there are n+1 processors in the system. It improves on the previous emulation, which required O(n 2) messages (for each read or write operation). The message complexity of the new emulation is within a constant factor of the optimum.The new emulation implies improved algorithms to solve the following problems in the message-passing model in the presence of processor failures: multi-writer multi-reader registers, concurrent time-stamp systems, ℓ-exclusion, atomic snapshots, randomized consensus, implementation of data structures, as well as improved fault-tolerant algorithms for any solvable decision task.