Efficient and reliable VLSI algorithms and architectures for the discrete Fourier transform

Abstract

The design of both area-efficient and reliable VLSI arrays for computation of the complex N-point discrete Fourier transform (DFT) is considered. C.D. Thompson's VLSI model of computation (1979) is used to quantify the area required by wiring and the achievable period. Four architectures using the fast two-dimensional (2-D) algorithm for the DFT that achieve the maximum throughput per chip area are presented. The first two use N-element 2-D meshes requiring N+2N/sup 3/2/ multiplications and 1+2 square root N periods per DFT. The first uses in place data I/O and can be made systolic with Goertzel's algorithm. The second is systolic with row parallel I/O. The third and fourth architectures both use pipelined DFT blocks of length square root N connected by a pipelined matrix transposer. The third uses systolic 2-D meshes for the short DFTs with period square root N. The fourth uses pipelined butterfly networks implementing standard FFT algorithms for the short DFTs, but only N(1+log/sub 2/ N) multiplications per DFT, thus preserving maximum throughput per unit area. The technique of algorithm-based fault-tolerance applies directly to all four architectures with only fractional redundant overhead. >