Efficient and low latency turbo encoder design using Verilog-Hdl

Abstract

Low complexity turbo-like codes based totally on the simple trellis or simple graph shape consequences in encoding with low complexity. Out of this Convolution, encoder and turbo codes are widely used due to the splendid errors control performance. The most famous communications encoding set of rules, the iterative deciphering calls for an exponential expansion in hardware complexity to acquire expanded encode accuracy. This paper makes a usage of Log-Map based Iterative decoding technique and specialty in the conclusion of the turbo encoder. The rapid codes are designed with the help of Recursive Systematic Convolution and are separated thru interleave, which (thing used to rearrange the bit collection) plays an essential position within the encoding technique. This paper offers the design of the parallel connection of Recursive Systematic Convolution (RSC) encoders and interleave to restrict postpone, results to form a turbo Encoder. The turbo Encoder is designed by way of Verilog-HDL and Synthesized through Xilinx ISE