Efficient adaptive RLFIR filter based on distributed arithmetic logic using reversible gates

Abstract

This brief presents an efficient adaptive Reversible Logic Finite Impulse Response filter (RLFIR) based on Distributed Arithmetic (DA) using Reversible gates. Reversible logic is one of the most essential issues at present time due to its power reduction effectiveness in circuit designing. The delay and the logical resources of the proposed design were significantly reduced by using add one carry select adder in the inner product of the adaptive filter. The existing carry save adder in the adaptive filter is replaced by the proposed add one carry select adder and logic gates in add one carry select adder is replaced by reversible logic gates in order to reduce the power consumption. The logical resources and delay is reduced to half when compared to the existing carry save adder and the power consumption is reduced to half by changing reversible gates. This paper presents quantum implementation and combinational circuit of all basic reversible gates and its VHDL code. All reversible logic gates are verified and simulated by Xilinx 8.2i.