Abstract
A cascaded S-parameter method is proposed in this paper for high-speed data rate signal integrity analysis of Through Hole Via and Traces in a multilayer printed circuit board (PCB). This methodology enables efficient and accurate construction for 3D simulation with physical based model for complex multilayer PCB structures with multiple vias transition into longer traces length and RF connectors. PCB with connectors or IC packages are ‘cut’ into ‘sections’ to model in 3D full wave FEM solver (HFSS 3D Layout), and S-parameters are extracted from each model, these models are analyzed by cascading the S-parameters in ANSYS Electronics Desktop Circuit environment and compare with full PCB with connectors structure. In this paper, a 2-inch Differential Pair Channel test structure with RF connectors will be fabricated and validated by both simulations (ANSYS HFSS and Electronics Desktop) and measurements with frequency range from DC to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$50GHz$</tex> .
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