Abstract

SiC-based diodes and mosfet s switch extremely quickly with low conduction losses. Thus, from the perspective of efficiency, such devices are ideal for a continuous conduction mode (CCM) boost power factor correction (PFC) converter. However, the circuit parasitic becomes alive while switching with high $dv/dt$ and $di/dt$ values, which necessitates the need for electromagnetic compatibility (EMC) compliance measurements. Employing the best available low-loss SiC mosfet and SiC diode, in this paper, a 1-kW PFC boost converter prototype was designed, developed, and evaluated with the objective of quantifying the efficiency and EMC signature. The efficiency is evaluated through two approaches, namely, a circuit simulation and a laboratory measurement. With the first approach, the switching losses are obtained using a widely accepted double-pulse test methodology, and the conduction losses are taken from the data sheet, whereas with the second approach, the current and voltage are recorded at the input and output of the PFC converter using power analyzer. The electromagnetic interference (EMI) is monitored using line impedance stabilizing network and EMC analyzer. To maximize the efficiency, a fast, clean switching of the silicon carbide (SiC) is necessary. Utilizing a low-parasitic printed circuit board design approach and switching the selected low-loss SiC devices with a 0 $\Omega$ external gate drive resistance, this PFC boost yields a peak efficiency of 97.2% at full-rated power when switched at 250 kHz. Furthermore, the EMI noise was measured at 66 and 250 kHz. It was found that the same EMI filter size satisfies the CISPR 11 Class B conducted EMI limit at both switching frequencies with a noise of approximately 10 dB higher at 250 kHz. As the main contribution of this paper, the best case efficiency and worst case EMI are evaluated in this paper.

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