Abstract

Semiconductor manufacturing technology has shifted towards finer design rules, and demands for critical dimension uniformity (CDU) of resist patterns have become greater than ever. One of the methods for improving CDU of resist pattern is to control the temperature of post-exposure bake (PEB). When ArF resist is used, there is a certain relationship between critical dimension (CD) and PEB temperature. By utilizing this relationship, Resist Pattern CDU can be improved through control of within-wafer temperature distribution in the PEB process. We have already applied this method to Resist Pattern CDU improvement and have achieved these results. In this evaluation, we aim at: 1. Clarifying the relationship between the improvement in Resist Pattern CDU through PEB temperature control and the improvement in Etching Pattern CDU. 2. Verifying whether Resist Pattern CDU improvement through PEB temperature control has any effect on the reduction in wiring resistance variation. The evaluation procedure is: 1. Preparation of wafers with base film of doped Poly-Si (D-Poly). 2. Creation of two sets of samples on the base, a set of samples with good Resist Pattern CDU and a set of samples with poor Resist Pattern CDU. 3. Etching of the two sets under the same conditions. 4. Measurements of CD and wiring resistance. We used Optical CD Measurement (OCD) for measurement of resist pattern and etching pattern for the reason that OCD is minimally affected by Line Edge Roughness (LER). As a result, we found that; 1. The improvement in Resist Pattern CDU leads to the improvement in Etching Pattern CDU . 2. The improvement in Resist Pattern CDU has an effect on the reduction in wiring resistance variation. There is a cause-and-effect relationship between wiring resistance variation and transistor characteristics. From this relationship, we expect that the improvement in Resist Pattern CDU through PEB temperature control can contribute to device performance improvement.

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