Effects of wafer cooling characteristics after post-exposure bake on critical dimensions

Abstract

VLSI design rules require existing LSI design rules to extend to sub-micron and half-micron geometries. Using high resolution resist and 5X stepper (G- line) technology along with a Post-Exposure Bake (PEB) is a common method to improve the resolution. The PEB drives out residual photoresist solvents which can interfere with the develop process, resulting in CD variations. PEB strongly influences CD variations. The authors consider the following PEB parameters in this CD improvement study: (1) altering the PEB temperature, (2) altering the PEB time, and (3) altering the queuing time between PEB and cool prior to develop. The process characterization data includes critical dimension data for 0.8 micrometers lines, including proximity effects data on four high-resolution photoresists.