Effects of thermal annealing on electrical characteristics of Cd/CdS/n-Si/Au–Sb sandwich structure

Abstract

In general, at the metal–semiconductor contacts, interfacial layers have been fabricated by different methods such as molecular beam epitaxy, metal organic chemical vapor deposition, sputtering and vacuum evaporation. However, all of these techniques have encountered various difficulties in the deposited films. Instead of these methods, since Successive Ionic Layer Adsorption and Reaction (SILAR) method is simple, fast, sensitive, and less costly to prepare interfacial layer, we have first employed this method in order to prepare Cd/CdS/n-Si/Au–Sb sandwich structure. For this reason, the CdS thin film has been directly formed on n-type Si substrate by means of SILAR method. The Cd/CdS/n-Si/Au–Sb sandwich structure has demonstrated clearly rectifying behaviour by the current–voltage ( I– V) curves studied at room temperature. In order to observe the effect of the thermal annealing, this structure has been annealed at temperatures from 50 to 300 °C for 3 min in N 2 atmosphere. The characteristic parameters such as barrier height, ideality factor and series resistance of this structure have been calculated from the forward bias I– V characteristics as a function of annealing temperature with different methods. The values of n, Φ b and mean R s of the initial Cd/CdS/n-Si/Au–Sb sandwich structure were found to be 2.31, 0.790 eV and 1.86 kΩ respectively. After annealing at 300 °C, these values were changed to 1.89, 0.765 eV and 0.48 kΩ. It has been seen that the barrier height, ideality factor and series resistance have slightly changed with increasing annealing temperature up to 300 °C.