Effects of the Timing of AC Stress on Device Degradation Produced by Trap States in Low-Temperature Polycrystalline-Silicon TFTs

Abstract

Device degradation under ac stress in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed with the density of trap states, electron-emission time, and electron-trapping time as foci. LTPS TFTs are shown to incur greater deterioration of characteristics under ac stress than silicon-on-insulator TFTs. Characteristics are more rapidly worsened as the falling time (t/sub f/) of gate pulses becomes shorter in the range below 1 ms. In addition, the degradation produced by a given number of pulses increases with the duration of the low level of the gate pulse in the range up to 1 ms. These behaviors are due to the slow emission of trapped electrons. On the other hand, the device degradation is independent of the duration of the high level of the gate pulse because the electrons are trapped quickly (in less than 1 /spl mu/s) once the level on the gate becomes high. The U-shaped distribution of trap-state density within the energy gap largely determines the dependence of the ac stress degradation on t/sub f/, since trapped electrons for which the emission time is longer than t/sub f/ are not emitted within the period of transient variation of gate voltage, and the number of electrons emitted after the gate has gone low increases with decreasing t/sub f/. Severe degradation is induced by ac stress conditions that correspond to electron emission from the trap states close to conduction band when the TFT is turned off.