Effects of Substrate Structure on the Warpage of Flip Chip IC Packages

Abstract

Warpage after the encapsulation process is a big concern for the plastic IC packaging industry. Too large warpage in a package will cause serious problems, including lower package reliability and, difficulty with post encapsulation processes such as reflow, etc. Thus, accurate prediction of warpage after the encapsulation process is desirable and a number of research works have been done in this area. Most previous researchers have focused on thermal-induced warpage analyses considering only the effects of differences in the thermal expansion coefficients between constituent materials and have neglected cure-induced shrinkage effects. However, epoxy molding compound (EMC) is a thermosetting plastic material, and the colloids will cause volumetric shrinkage due to cure reactions after heating. Ignoring cure-induced volume change effects will cause miscalculations in the amount of warpage, so it is necessary to take into account cure-induced shrinkage in analyses. Therefore, volume shrinkage caused by both EMC cure and temperature effects are considered in this paper.A flip chip IC package is a package with a substrate. Most substrates in a flip chip IC are made of layers of printed wire board materials with different thermal expansion coefficients, such as FR4 or core material, Cu, green paint, and solder mask, etc. Therefore, it is also possible to observe volume shrinkage in a substrate due to cure and thermal effects. However, to simplify the problem, the degree of cure of the substrate is assumed to be fully cured during packaging, so cure-induced shrinkage of substrates is ignored in this paper. Only volume changes due to temperature effects are considered for the substrate. The analysis started with a mold filling simulation, and using the data for the package temperature and pressure, warpage simulations were executed.EMC properties were obtained using various standard test techniques. The Cross Castro-Macosko viscosity model was used in this paper. Kamal’s cure kinetic model was also used, which was measured with a differential scanning calorimeter (DSC). Cure-induced volume changes were expressed with the P-V-T-C equation, which describes the relationship between changes in the cure-induced volume, degree of cure, pressure, and temperature. Determination of the coefficients in the P-V-T-C equation were done by combining the data from a P-V-T-C test machine and the cure kinetic model.Using the actual engineering applications to verify the feasibility of the analytical method, it was found that for a flip chip package, warpage analysis considering both cure and thermal-induced shrinkage is more accurate than that considering thermal expansion only. The results also showed that both the EMC cure shrinkage and substrate design play a significant role in warpage analyses for flip chip IC packages.