Abstract

The chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layer, to be applied to integrated circuits for deep submicron technology. Despite increased use of CMP process, it is difficult to accomplish defect-free global planarization in interlayer dielectrics (ILD). Especially, defects like microscratches lead to severe circuit failure and affect yield. CMP slurries sometimes contain particles exceeding 1.0 μm size, which can cause microscratch on a wafer surface. The large-sized particles in these slurries may be caused by particle agglomeration in slurry supply line. Filtration has been recommended in oxide CMP process in order to reduce these defects. In this work, we have systematically studied the effects of filtration and the defect distribution as a function of polished wafer counts by using various filters in the ILD–CMP process. Filter installation in CMP polisher effectively reduced the defect density after ILD–CMP process. The experimental results show that the slurry filter plays an important role in determining the consumable pad lifetime. Furthermore, the filter lifetime is dominated by the defect counts. We have concluded that the degree of generated defects is determined by slurry filter lifetime.

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