Effects of silicon layer properties on device reliability for 0.1-μm SOI n-MOSFET design strategies

Abstract

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-/spl mu/m SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10/sup 16/ cm/sup -3/) channel and 2) a heavily-doped (10/sup 18/ cm/sup -3/) channel. For each design, the silicon layer thicknesses (T/sub Si/) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO/sub 2/ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T/sub Si/ results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead.