Effects of SILAR cycle on the electrical characteristics of Cd/CdSe/n-Si/Au-Sb structure

Abstract

Cd/CdSe/n-Si/Au-Sb structures have been fabricated by Successive Ionic Layer Adsorption and Reaction (SILAR) method under various SILAR cycles. The characteristics parameters of these structures such as barrier height, ideality factor, series resistance are calculated from the current-voltage (I-V) measurements and the barrier height, carrier concentration are calculated from reverse bias capacitance-voltage (C-V) measurements at 300 kHz frequency and room temperature. Furthermore, the density distribution and rectifying ratio of these structure have been calculated from the I-V measurements as a function of SILAR cycle. It has been seen that the changes of characteristic parameters such as barrier height, ideality factor and series resistance of the Cd/CdSe/n-Si/Au-Sb structures have lightly changed with increasing SILAR cycle.