Effects of Process and Environmental Variations on Adder Architectures

Abstract

Scaling of the on-chip feature size and power supply voltage have significantly reduced the noise margins of an integrated circuit and have aggravated the effects of process and enviromental variations. These effects can introduce delay variations on the signals within a circuit, possibly causing a violation of the timing constraints in a clocked register that can lead to system malfunctioning. The effects of parameter variations on the timing characteristics of adder structures are investigated in this paper. The sensitivity of the critical delay of sum and carry signals under variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different adder architectures.