Abstract
Performance degradation of n-MOSFETs with plasma-induced recess structure was investigated. The depth of Si recess (dR) was estimated from the experiments by using Ar gas plasmas. We propose an analytical model by assuming that the damage layer was formed during an offset spacer etch. A linear relationship between threshold voltage shift (DeltaVth) and d R was found. Device simulations were also performed for n-MOSFETs with various (dR). Both |DeltaVth| and off-state leakage current increased with an increase in d R . The increase in |DeltaVth| becomes larger for smaller gate length. The results from device simulations are consistent with the analytical model. These findings imply that the Si recess structure induced by plasma damage enhances Vth-variability in future devices.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
