Effects of oxidation process on the tunneling barrier structures in room-temperature operating silicon single-electron transistors

Abstract

We investigate the tunneling barrier structures in the room-temperature operating silicon single-electron transistors (SETs). The devices are fabricated in the form of the point-contact channel metal-oxide-semiconductor field-effect transistors with gate oxide formed by thermal oxidation or low-pressure chemical vapor deposition (LP-CVD). From the gate voltage and temperature dependence of the peak current in the SET characteristics, it is found that the thermal oxidation process leads to higher and narrower tunneling barriers. In some SETs with CVD-deposited gate oxide, thermally activated conduction over the low tunneling barriers is clearly observed in a wide temperature range from 100 K-300 K.