Effects of Oxidation and Annealing Temperature on Grain Boundary Properties in Polycrystalline Silicon Probed Using Nanometre-Scale Point-Contact Devices

Abstract

We discuss a method to fabricate single-electron transistors targeted at high-temperature operation. Natural nanostructure in polycrystalline silicon was utilised for charging islands and its grain boundaries were modified by a multi-step annealing technique to form grain-boundary tunnelling barriers. The effects of oxidation and annealing temperature on individual grain boundary properties were investigated using point-contact devices. It is found that low temperature oxidation selectively oxidises the grain boundaries but does not affect carrier transport significantly. Subsequent annealing increases the grain-boundary tunnelling barrier height and resistance. In addition, their distribution is narrowed by optimizing the annealing condition. Introduction A single-electron transistor (SET) is a novel device where the on-off states can be formed by a single-electron, without any statistical fluctuation in electron number[1,2,3]. To realize practical single-electron circuits, it is vital to control tunnelling barrier properties. For example, total tunnel resistance (RT) should be less than ~1 GΩ if a single-electron is transferred at 1 GHz at the source-to-drain voltage (Vds) of 1 V. In addition, an RT value should be much larger than the quantum resistance (h/e=26kΩ) to avoid the quantum smearing[2]. Furuta et al. report that an RT value > 1 MΩ is required to obtain a large on-off ratio[4]. To suppress a leakage current at room temperature (RT), a charging energy (Ec) must be much larger than thermal energy kBT. Saitoh et al. indicate that an Ec value greater than 10 kBT (260 meV at RT) is favourable[5]. If a tunnelling barrier is made of 1-nm-thick a-SiO2, this condition corresponds to the cross-section area as small as 3 nm × 3 nm. Tunnel resistance calculation[6] suggested that we have to fabricate a very thin (< Tel. No.: 81-45-924-5357 Fax No.: 81-45-924-5339 e-mail: tkamiya@msl.titech.ac.jp 0.6 nm) tunnelling barrier if its height is as large as 3 eV, which is expected for the c-Si/a-SiO2 junction. Figure 1 indicates that a realistic tunnel barrier may be ~ 1 nm in thickness and 0.26-1.2 eV in height. It is not easy to form such small charging islands and thin tunnelling barriers by lithography techniques only. A promising idea to overcome these requirements is to use a naturally-formed nanostructure in a material, which includes very thin polycrystalline silicon (poly-Si)[7] and hydrogenated nanocrystalline silicon[8,9], where crystalline silicon grains work as charging islands and GBs work as tunnelling barriers. However, in general, the properties of individual GBs vary significantly, and it is difficult to control GB properties to conform the above guidelines. This article discusses a method to control GB tunnelling barrier properties in poly-Si. The effects of oxidation and thermal annealing on electrical properties of individual GBs were examined using nanometre-scale point-contact (PC) devices. We propose a multi-step annealing technique, which is consisted of two or more oxidation and subsequent annealing processes. This technique can separate the incorporation of oxygen in GBs and the modification of their properties temporary, providing better controllability for GB properties. Experimental Our poly-Si film was prepared by solid-phase-crystallization of a 50-nm-thick amorphous silicon at 850 C for 30 min[4]. The films were doped n type to 10 / cm using phosphorus ion-implantation. Transmission electron microscopy (TEM) indicated that the grains were columnar with lateral sizes from 20 nm to 150 nm. PC structures (30 nm wide and 40 nm long) with double side-gates were fabricated to investigate the local carrier transport properties (Fig. 2). The PC structures were defined by electron-beam lithography in PMMA resist, followed by reactive-ion-etching in a 1:1 plasma of SiCl4 and CF4[10]. 0 0.5 1 1.5 2 2.5 3 10 05 10 06 10 07 10 08 10 09 10 10 10 11 10 12 Barrier height / eV Tu nn el re si st an ce / oh m