Abstract
The implant anneal process for 6H-SiC self-aligned NMOS transistors will degrade the SiO/sub 2//SiC interface. The interface is of great concern because it reduces the performance of MOS transistors. The effect of anneal time and temperature on the effective oxide charge and interface state density is presented. The optimal anneal for self-aligned NMOS transistors is obtained by choosing the anneal condition with the highest implant activation that causes the least damage to the interface.
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