Effects of gate insulator using high pressure annealing on the characteristics of solid phase crystallized polycrystalline silicon thin-film transistors

Abstract

The oxidizing ambient was built using high pressure H2O vapor at 550 °C. For the solid phase crystallization (SPC) polycrystalline silicon (poly-Si) that is annealed for 1 h at 2 MPa, the oxide thickness is about 150 Å. The oxide layer is approximately 90 Å above the original surface of the poly-Si and 60 Å below the original surface. The oxide layer is used as the first gate insulator layer of thin-film transistors (TFTs). The heating at 550 °C with 2 MPa H2O vapor increased the carrier mobility from 17.6 cm2/V s of the conventional SPC process to 30.4 cm2/V s, and it reduced the absolute value of the threshold voltage (Vth) from 4.13 to 3.62 V. The subthreshold swing also decreased from 0.72 to 0.60 V/decade. This improvement is attributed mainly to the reduction in defect density at the oxide/poly-Si interface and in the poly-Si film by the high pressure annealing (HPA) process. Since the realization of excellent performance at the oxide/poly-Si interface and in poly-Si depends on the defect density, the poly-Si having the thermal oxide formed by a combined process of SPC and HPA may be well suited for fabrication of poly-Si TFTs for flat panel displays such as active matrix organic light emitting diodes.