Effects of electrical stressing in power VDMOSFETs

Abstract

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon /spl equiv/Si/sub o//sup /spl dot// defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps /spl equiv/Si/sub o//sup +/ to interface-trap precursors /spl equiv/Si/sub s/-H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects /spl equiv/Si/sub o//sup /spl dot//spl dot//Si/sub o//spl equiv/ is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors /spl equiv/Si/sub s/-H with the charged oxide traps /spl equiv/Si/sub o//sup +/spl dot//Si/sub o//spl equiv/ and H/sup +/ ions are proposed to be responsible for interface trap buildup.