Effects of Drain Bias on Memory-Compensated Analog Predistortion Power Amplifier for WCDMA Repeater Applications

Abstract

This paper represents the effects of drain bias on the linearity and efficiency of an analog pre-distortion power amplifier(PA) for wideband code division multiple access(WCDMA) repeater applications. For verification, an analog predistorter(APD) with three-branch nonlinear paths for memory-effect compensation is implemented and a class-AB PA is fabricated using a 30-W Si LOMaS. From the measured results, at an average output power of 33 dBm(lO-dB back-off power), the PA with APD shows the adjacent channel leakage ratio(ACLR, <TEX>${\pm}$</TEX>5 MHz offset) of below -45.1 dBc, with a drain efficiency of 24 % at the drain bias voltage(<TEX>$V_{DD}$</TEX>) of 18 V. This compared an ACLR of -36.7 dEc and drain efficiency of 14.1 % at the <TEX>$V_{DD}$</TEX> of 28 V for a PA without APD.