Effects of contamination on selective epitaxial growth

Abstract

As MOSFET dimensions scale down in size, it has become increasingly difficult to maintain high drive current while suppressing the off-state leakage current. One method of avoiding short-channel effects is to scale the source/drain (S/D) junction depths proportionally with the gate length. Unfortunately, this increases the S/D resistance, which slows the circuit. To keep the S/D junction shallow without affecting the S/D resistance, a raised S/D (RSD) structure is required. Integrating RSD can be difficult. Selective epitaxial growth (SEG) is the process used to incorporate RSD. This process requires a relatively clean surface to initiate the growth. Insertion of SEG earlier in the process flow facilitates selective epitaxial growth. Insertion of SEG later in the process flow results in higher levels of contamination at the interface of the Si substrate and the RSD structure. In this paper, we identify some mechanisms that determine the quality of the selective epitaxial film. Results indicate that Si defects are not a dominant mechanism in SEG film quality. Instead, results suggest that higher levels of contamination increased the surface roughness of the epitaxial film. PMOS regions were found to have higher levels of contamination and rougher epitaxial films than NMOS regions. Hydrogen bake as high as 900 °C was required to lower the surface contamination and provide excellent epitaxial morphology. Unfortunately, this high temperature causes enhanced dopant diffusion and deactivation of the device. Previous work [H. van Meer, K. De Meyer, Symposium on VLSI Technology Digest of Technical Papers, 2002, p. 170.] identified an alternative integration that provides excellent quality selective epitaxy, without dopant diffusion and deactivation.