Effects of Channel Width on Stress Enhancement for Damascene-Gate nFETs With Top-Cut Tensile-Stress Liner

Abstract

This letter provides channel-stress behavior results induced by a local strain technique which consists of the process combination of a damascene-gate and top-cut tensile stress SiN liner for narrow channel-width nFETs using 3-D stress simulations and demonstrations. The dummy-gate removal, which is an intrinsic step in the damascene-gate process, is found to enhance tensile channel stress along the gate length at the edge of the channel beside the shallow trench isolation. In consequence of a mobility boost due to the high tensile stress, drain-current enhancement in the saturation is achieved for the damascene-gate nFETs with the narrow channel width and short gate length.