Abstract

In this paper, we have investigated a circuit model of the on-wafer interconnects for high-speed CMOS integrated circuits (ICs). Along with increasing the operating frequency, there are various factors like chip size, circuit density, complexity, cost and delay which make interconnects an important issue that has to be considered while designing ICs. At GHz frequencies, long interconnect wires exhibit transmission line behaviour and also traditional lumped and distributed RC models of interconnects are no longer accurate and result in substantial errors in predicting delay and crosstalk. Therefore, a RLC circuit model of interconnects is consider in this work, which takes into account the effects inductance also. Two coupled interconnects are used to show the effects of both capacitive and inductive coupling. The coupled circuit model is studied in terms of S-parameters namely, S11 and S21, which gives return loss and insertion loss, respectively. The proposed circuit model is simulated by using the Advanced Design System 2005A (ADS) by Agilent Technologies. These parameters are obtained for different cases considering both types of coupling collectively and individually.

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