Abstract
Maximum-Likelihood (ML) decoding has been proven to fully exploit the corrective capabilities of a code, especially at very low Bit Error Rates (BER), avoiding pitfalls of approximate iterative decoding methods. However, there are huge barriers that inhibit the hardware development of realistic realizable Soft-Decision ML decoding algorithms for long block codes, due to the fact that this approach is known to be NP-hard [1]. The most significant obstacle is the computation of a large number of Euclidean squared distances between a received word and candidate codewords, which requires a large number of additions and multiplications. This part of the decoder usually increases the critical path of the complete system by a significant amount and uses a lot of hardware. The effect becomes prominent when the decoding process is parallelized, which is often the case in Soft-Decision ML decoders. Although many efficient addition and multiplication hardware schemes have been proposed, they do not make a big impact on this specific problem. In this paper, we present a simplified implementation for the computation of the Euclidean squared distance, by utilizing a property for the squaring of binary numbers, which is found to reduce the word length of subsequent hardware operations. The impact of the proposed method is illustrated by its application to an ML decoder. The effectiveness of the decoder is not compromised by any of the simplifications introduced. Synthesis results using the proposed method, targeting a Virtex-5 XC5VFX70T device, reveal hardware complexity reductions of the order of 30%, with no performance penalty; in fact maximum clock frequency is increased by 4%. Since the percentage of improvement varies, depending on the length of the input symbols, we also derive parametric complexity formulas to express this dependence. Finally, we present some figures relevant to the power consumption improvements achieved by the proposed technique and corresponding circuits.
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