Abstract
Today's commonly used macro generators provide for read/write memories of type SRAM, Register File, Multi-Port RAM, Single-Order Addressed Memory (e.g. FIFO), CAM (Content Addressable Memory), etc. In addition to automatically generating the required momory, the appropriate test, which may be applied externally or internally as a BIST, has to be determined. Current literature provides tests for most memory types; however, tests for single-order addressed (SOA) memories, whereby the address can only change in one direction (e.g. from address 0 ton-1) have not been published yet. SOA memories are used in FIFOs and in applications where the BIST area overhead and/or speed penalty for normal (dual) order addressing are not acceptable. This article illustrates the testing problems and presents a family of march algorithms optimized for testing SOA memories.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.